Albany, NY and Austin, TX (14 October 2008) – SEMATECH engineers and the industry at large have made significant advances in moving forward the infrastructure that will prepare extreme ultraviolet lithography (EUVL) for cost-effective manufacturing, according to papers presented at the 2008 International EUVL Symposium in Lake Tahoe, California.
At the seventh EUVL Symposium, an outstanding set of 52 technical papers and 106 posters covering all aspects of EUVL technology, reported excellent progress in many key areas. At the same time, presenters highlighted various technology, infrastructure, and business challenges that the industry needs to address to successfully insert EUVL into manufacturing at the 22 nm half-pitch node.
The forum keynote addresses – “EUV Lithography’s Future,” by Dr. Harry Levinson of AMD, and “Samsung’s Lithography Strategy,” from Dr. Woosung Han of Samsung – emphasized that EUVL technology has transitioned from the research phase to the development phase, and is now focused on early device and yield learning and pre-production tooling to prepare EUVL for pilot line insertion in the 2010-2012 timeframe.
Experts reported, for the first time 45 nm node yielding full-field SRAM’s produced using EUV lithography. A presentation by a chip manufacturer illustrated how EUVL contact hole printing for 3X nm half-pitch nodes and line and space printing for 2X nm hp nodes are significantly more cost effective than competing technologies, in part because little or no optical proximity correction (OPC) is needed.
Full field tool imaging, using conventional illumination, has demonstrated 28 nm half-pitch line and space resolution and 28 nm 1:1 contact hole resolution without using OPC. Further data showing ~1 nm intrawafer critical dimension uniformity (CDU) for 35 nm hp 1:1 lines and spaces clearly demonstrate the excellent imaging performance of EUVL alpha tools.
Critical progress has also been made in EUV sources. A fully integrated laser produced plasma (LPP) source collector module with effective mitigation of tin deposition and ion erosion was demonstrated with 3 to 4 W at intermediate focus (IF). Also, generated EUV power for discharge produced plasma (DPP) sources—the type that currently is used in alpha tools—has tripled to 500W.
SEMATECH researchers and research partners highlighted the key role the consortium has played in achieving significant advances in EUV resists in papers presented at the symposium. Specifically, SEMATECH researchers have demonstrated 20 nm resolution images and 30 nm 1:1 contact hole images and have achieved feature resolution for both, as confirmed by cross-section scanning electron microscopy images.
The resist technology research leading to these accomplishments has been enabled by SEMATECH’s EUV Resist Test Center (RTC) at the College of Nanoscale Science and Engineering’s (CNSE) Albany NanoTech Complex in Albany, NY, and by its micro-exposure tool (MET) located at the Berkeley Advanced Light Source (ALS) Lab at University of California, Berkeley. Supported by SEMATECH’s MET exposure capabilities, resist suppliers have been able to address the challenges of simultaneously meeting resolution, line edge roughness (LER), and sensitivity targets in a systematic way.
“Good progress has been made toward achieving resist resolution and sensitivity targets, with some improvement in line edge roughness, and now chip manufacturers are demonstrating post-exposure resist processes that lead to significantly reduced line edge roughness,” said Stefan Wurm, EUVL Symposium chair and SEMATECH’s associate director of Lithography. “With the world’s leading-edge exposure tool for EUV resists learning, SEMATECH continues to enable the development of high performance resists required to demonstrate EUV manufacturability to our member companies and the industry.”
Furthermore, SEMATECH also reported it has significantly reduced printable substrate defects with its development of a new and fast defect-removing cleans process. Combining a 6X faster two-hour defect smoothing process, this constitutes a major step forward in enabling cost efficient low-defect mask blank manufacturing solutions. EUV mask blanks are now commercially available with approximately 5 defects at 73 nm size. To achieve the pilot line target of eight defects at 18 nm, the industry will require more sensitive defect inspection tools for mask substrates and blanks.
Lastly, SEMATECH’s aerial imaging and inspection research tool (AIT) at the Berkeley ALS Lab demonstrated that it is capable of resolving 88 nm mask features (22 nm half-pitch on the wafer). It is the only tool, world-wide, that allows chip manufacturers to characterize mask defect in an aerial imaging mode at this high resolution. However, to support pilot line operation and EUVL transition into manufacturing, a commercial EUV aerial imaging tool will be required for patterned mask defect review.
Given these significant advances, the EUVL Symposium Steering Committee identified at the conclusion of the conference three remaining focus areas that the industry needs to work on to enable EUVL manufacturing insertion:
The 2008 EUVL Symposium, held Sept. 29-Oct. 1, was organized by SEMATECH in cooperation with Selete, EUVA, and the EUV Cluster Steering Council.