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SEMATECH Announces Breakthroughs in High-Mobility Channels, Scaled High-k Gate Stacks, and Future Non-Volatile Memories

Experts to present significant progress on key next-generation technologies at VLSI‑TSA

HSINCHU, Taiwan (27 April 2009) –Experts from SEMATECH’s Front End Processes (FEP) program will present breakthrough research results in advanced logic and future non-volatile technologies at the International Symposium on VLSI Technology, System and Applications (VLSI-TSA) on April 27-29, 2009 at the Ambassador Hotel in Hsinchu, Taiwan.  The papers report progress in areas such as next generation high-k/metal gate (HKMG) materials, advanced flash memory, planar and non-planar CMOS technologies and HKMG defect metrology.

“Through collaborative research, our goal is to develop and characterize cutting-edge new materials and device structures that enable scaling logic, memory, and emerging technologies,” said Raj Jammy, SEMATECH’s vice president of Emerging Technologies. “SEMATECH’s work has always blended innovation with practical solutions to move the industry forward. We are happy to be sharing our results with an august community of technologists assembled in Taiwan, which plays an increasingly significant role in propelling the semiconductor industry toward future generations.”

SEMATECH papers to be delivered at VLSI include:

Monday, April 27

  • La-doped Metal/High-K nMOSFET for Sub-32nm HP and LSTP Application – Investigates the suitability of nMOSFETs with the La-doped high-k/metal gate stack to see its suitability for sub-32nm low standby power (LSTP) and high performance applications.
  • Extending spectroscopic ellipsometry for identification of electrically active defects in Si/SiO2/high-k/metal gate stacks – Explores a new method using spectroscopic ellipsometry to non-invasively identify oxygen vacancy defects in the bottom interfacial SiO2 layer of the scaled high-k/metal gate stacks.
  • Reliability Assessment of Low Vt Metal High-k Gate Stacks for High Performance Applications – Describes of reliability characterization techniques and models targeting HKMG lifetime predictions.
  • Additive Mobility Enhancement and Off-State Current Reduction in SiGe Channel pMOSFETs with Optimized Si Cap and High-k Metal Gate Stacks – Demonstrates high mobility pMOSFETs with high quality epitaxial SiGe films selectively grown on Si (100) substrates.

Wednesday, April 29

  • Band Engineered Tunnel Oxides for Improved TANOS-type Flash Program/Erase with Good Retention and 100K Cycle Endurance – Demonstrates, for the first time, that band-engineered tunnel oxides integrated with a high-k/metal gate can improve program, erase, and endurance in charge-trapped flash memory devices.
  • High Mobility SiGe Shell-Si Core Omega Gate PFETs – Explores the use of Omega gate-type pFETs with a SiGe shell (high mobility channel) on a Si core.

Serving as the bridge between R&D and manufacturing, SEMATECH drives pre-competitive cooperation and collaboration to accelerate the commercialization of nanoelectronics and nanotechnology.  SEMATECH’s FEP engineers are focused on developing new techniques for extending high-k dielectrics, metal gates, high mobility channels, and advanced memory technologies in collaboration with member companies, universities, national labs, and supplier partners.

The International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE), a leading professional association for the advancement of technology, in association with Taiwan’s Industrial Technology Research Institute (ITRI).  VLSI-TSA is one of many industry forums SEMATECH uses to collaborate with scientists and engineers from corporations, universities, and other research institutions.

 

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