HSINCHU, Taiwan (April 25, 2012) – SEMATECH experts reported on innovative approaches to realize advanced CMOS logic and memory device technologies and 3D through-silicon via (TSV) manufacturing at the International VLSI Technology, System and Applications Symposium (VLSI-TSA) on April 23-25, 2012.
Today nearly all electronic devices are built on complementary metal-oxide semiconductor (CMOS) technology. For over half a century, silicon-based materials have been the basic layers used in the manufacturing of CMOS transistors; however these staple materials, as well as materials derived from silicon such as insulators and contact metals, are reaching their limits as the industry looks to lower power dissipation in CMOS devices and as scaling approaches the physical limits of silicon transistors.
In a series of nine research papers, an international team of SEMATECH researchers reported on innovative materials and new transistor structures to address key aspects of transistor performance, power and cost. The papers, selected from hundreds of submissions, outlined leading-edge research in high-k/metal gate (HKMG) materials, resistive RAM (RRAM) memory and planar and non-planar CMOS technologies.
“Through intense research and development efforts, SEMATECH is developing manufacturable solutions and practical implementation approaches for innovative materials in future transistor structures,” said Raj Jammy, vice president of Emerging Technologies. “The research that was presented at VLSI TSA demonstrates SEMATECH’s leadership in developing new materials, processes and concepts that will pave the way for emerging technologies.”
One potentially industry-changing technology, a direct metal bonding interconnect approach, was introduced by Sitaram Arkalgud, director of SEMATECH’s 3D Interconnect program. In order for 2.5D and 3D integration to reach its full potential, chip-to-interposer and chip-to-chip interfaces have to support a very large number of power and signal connections. Today most solder-based interconnect schemes will not scale sufficiently due to mechanical, electrical, thermal and reliability limitations.
Arkalgud revealed SEMATECH’s copper-to-copper direct bonding (CuDB) technology as a promising technology to aggressively scale chip-to-chip interconnects and keep pace with advances in TSV. He also discussed recent progress and remaining technical and economic hurdles in moving toward high-volume manufacturing of CuDB interconnects.
SEMATECH technologists also reported technical advances in the following areas:
SEMATECH's Front End Processes program, located at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany, is exploring innovative materials, new transistor structures, and alternative non-volatile memories to address key aspects of system-level performance, power, variability and cost, and to help accelerate innovation in the continued scaling of logic and memory applications.
The International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) is sponsored by Taiwan’s Industrial Technology Research Institute (ITRI) in association with Institute of Electrical and Electronics Engineers, or IEEE, a leading professional association for the advancement of technology. VLSI-TSA is one of many industry forums SEMATECH uses to collaborate with scientists and engineers from corporations, universities and other research institutions, many of whom are research partners.