SEMATECH DOC ID #: 98013452A-TR

Title: Test Structures for Benchmarking the Electrostatic Discharge (ESD) Robustness of CMOS Technologies

Author(s): Robert Alexander;

Document date: 02/25/1998

Descriptor(s): test structures;electrostatic discharges;CMOS;semiconductor diodes;

Abstract:  This document defines a set of standard test structures with which to
benchmark the electrostatic discharge (ESD) robustness of CMOS technologies.
The test structures are intended to be used to evaluate the elements of an
integrated circuit in the high current and voltage ranges characteristic of
ESD events. Test structures are given for resistors, diodes, MOS devices,
interconnects, silicon control rectifiers, and parasitic devices. The
document explains the implementation strategy and the method of tabulating
ESD robustness for various technologies.

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