SEMATECH Workshop on Stress Management for 3D ICs Using Through Silicon Vias
16 March 2010
Albany, NY
Management of mechanical stresses is one of the key enablers for the successful implementation of 3D integrated circuits using Through Silicon Vias (TSVs). Copper-filled TSVs and wafers thinned to a few tens of microns introduce new reliability challenges, modify the stress profiles in the silicon, and may exacerbate the stresses introduced by tier-to-tier bonding and chip-package interactions. These stresses have the potential to modify device characteristics, affecting functional and parametric yield and reliability.
The stress-related impact of the processing done at the various stages in the manufacturing supply chain needs to be characterized and shared, and designers need a DFM-like solution for managing stress. The goal of this workshop is to identify and address the stress-related issues involved in using 3D-TSV.
There are many different approaches to implementing 3D. They all require an analysis of the mechanical stresses, and that analysis may be decisive in determining which approach is chosen for which application. This workshop will consider a “via-middle” approach which uses copper-filled TSVs formed after the front end of line (FEOL) and before the back end of line (BEOL), with die-to-wafer (DTW) stacking; this approach is expected to be particularly sensitive to mechanical stress.
Who Should Attend
This workshop is intended for IC designers and manufacturers; TSV technology developers; electronic design automation (EDA) experts; and semiconductor assembly and test service providers.
