Manufacturing and Reliability Challenges for 3D ICs using TSVs

September 25-26, 2008
San Diego, CA

Presentations

 
Applications for TSV and Issues for Adoption E. Jan Vardaman, TechSearch International Inc.
Challenges and Opportunities for Exploiting 3D Technology in System Designs Dr. John U. Knickerbocker, IBM Corporation
Reliability of TSV Technology E. Kaulfersch, Fraunhofer ENAS
3D Through Silicon Stacking for Mobile/Wireless Markets - Gaps and Challenges Matt Nowak, Qualcomm
3D-IC Fabrication Challenges for More Than Moore Applications Peter Ramm, Fraunhofer IZM
MEMS Sensor/IC Integration for Miniaturized TPMS (e-CUBES) Maaike. M.V. Taklo, Sintef
A Novel Approach to TSV Metallization based on Electrografted Copper Nucleation Layers Claudio Truzzi, Alchimer
Electroplating aspects in 3D IC Technology Albrecht Uhlig, Atotech
TSV Processing and Wafer Stacking Kathy Cook, Suss MicroTech
Die Cavity Integration Technology for Through-Silicon-Vias Stacking Katsuyuki Sakuma, IBM Corporation
Thermal and Stress Analysis Modeling for 3D Memory over Processor Stacks John McDonald, RPI
Thermo-Mechanical Analysis of Through Silicon Vias in 3D Integration Gary K.H. Lu, University of Texas
Through Silicon Vias (TSV): Physical Design and Reliability Sergy Savastiouk, AllVia

Posters

 
High-speed Copper Filling for 3D Packaging in Wafer Level Mizuki Nagai, Ebara Corporation
Low Cost Solutions to Challenges in Commercialization of Through-Silicon Via 3D Integration Alex Wang, Tango Systems
A New CVD Copper Process for TSV Metallization John Norman, Air Products
Issues Involved in Etching Through Silicon Vias at High Rate for Reliable Interconnects Leslie Lea, Surface Technology Systems
Failure Mechanisms of Wafer Bonding Thorsten Matthias, EVG
Processing of Thin Wafers using a Carrier wafer and Temporary Bonding and Debonding Thorsten Matthias, EVG
Remote Cold Dry Etching: Pre-Assembly Processes for Ultra-Thin Chips Peter Heinze, PVA-Tepla
Modifying Bosch etch process for improved CoO Brad Eaton, Applied Materials