Second SEMATECH Workshop on Stress Management for 3D ICs using Through Silicon Vias

July 13, 2010
San Francisco, CA

Welcome	Larry Smith, SEMATECH
Tech Tuning - Stress Management for 3D Through-Si-Via-Stacking Technologies	Riko Radojcic, Qualcomm
3D TSV Technology: Stress Assessment for Chip Performance	Valeriy Sukharev, Mentor Graphics
Materials Characterization for Stress Management	Ehrenfried Zschech, Fraunhofer
TSV Induced Stress Modeling	Paul Marchal, IMEC
Modeling TSV Stress Impact on Performance and Realibility	Xiaopeng Xu, Synopsys
Profiling of Process-induced Stress in Cu Through-Silicon Vias (TSVs) for Wafer-scale, 3D Integration	Robert Geer, CNSE
Remnant Stress/Strain in D-LSls with TSV's Fabricated by Wafer Thinning and Bonding	Mitsumasa Koyanagi, Tohoku U
Workshop Summary
Speaker Bios