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7th Annual SEMATECH Symposium Japan

22 June 2011
Tokyo, Japan

* Additional presentations will be made available following the Symposium. Please note, however, that not all presentations will be available.

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Plenary Session

  
Technology and Manufacturing Innovations:  New SEMATECH Initiatives Daniel Armbrust, SEMATECH
Supply Chain Management in Electronics Industry Akira Minamikawa, iSuppli
More than Moore or More Moore: a SWOT Analysis G. Dan Hutcheson, VLSI Research

Pushing the Patterning Limits: Advances in EUV Lithography 

  
EUVL Development at SEMATECH Bryan Rice, SEMATECH
EUV Photoresist Development Shinji Tarutani, Fujifilm
EUVL Mask: Progress and Challenges Naoya Hayashi, DNP
EUV LDP sources: Status and Roadmap Kunihiko Kasama, Ushio
EUV Resist Development at TOK Jun Iwashita, TOK
EUV Lithography into Production at Chipmakers: Update on ASML's NXE Platform Junji Miyazaki, ASML
The EUV Puzzle Gilroy Vandentop, Intel

CMOS Scaling: It’s a 3D World!

  
Development of 32nm CMOS and Recent Trends for Beyond 32nm Masaaki Niwa, University of Tsukuba
Towards 3-dimensional CMOS Scaling Kah-Wee Ang, SEMATECH
3D CMOS Devices - Why do we need them and challenges Tetsuo Endoh, Tohoku University
High Mobility Ge Devices as Alternative to Si  Akira Toriumi, University of Tokyo 
III-V CMOS Richard Hill, SEMATECH

Accelerating Momentum: Innovation and Collaboration in the 450 mm Transition

  
450 mm: Progress, Plans, and Strategy Tom Abell, SEMATECH/Intel 
450 mm Wafer Handling / Carrier Development  Poshin Lee, Entegris
Bare Wafer Particle Inspection for 450 mm Kazunori Nemoto, Hitachi High-Technologies Corp.
450 mm LPCVD Equipment Preparedness and Process Readiness of Eugene Technology Scott Youn, Eugenetech
450 mm Scalability of Plasma-enhanced CVD and ALD Nobuyoshi Kobayashi, ASM 

Safe and Robust Qualifications: Intelligent Statistical Methods
Intelligent Statistical Methods for Safer and More Robust Qualifications Wayne J. Levin, Predictum

Realizing the Potential: Driving 3D Into Mainstream Manufacturing
Overview of ITRI’s TSV Technology M. J. Tsai, ITRI
3D TSV Interconnects – SEMATECH Sitaram Arkalgud, SEMATECH
TSV Wafer Thinning Eiichi Yamamoto, Okamoto
Current Status of Packaging Materials for 3D Integration Hitoshi Kawaguchi, Sumitomo Bakelite Co.,  Ltd.
Low-Temperature Homo/Heterogeneous Bonding in Ambient Air for Future 3D-TSV Akitsu Shigetou, National Institute for Materials Science
3D Enablement Center Larry Smith, SEMATECH

Emerging Technologies: It’s a Smart, Dense, Functional World!
Non-charge Storage Resistive Memory: How It Works Gennadi Bersuker, SEMATECH
Recent Advances and Prospects in ReRAM Technology: Smart Electronics Application of Functional Oxides Hiro Akinaga, AIST
CMOS Scaling Beyond FinFETs: Nanowires and TFETs Chris Hobbs, SEMATECH
Functional NEMS Elad Alon, University of California, Berkeley

The Industry’s Enabler: Perspectives on Metrology Challenges
Metrology Program Overview Phil Bryson, SEMATECH
Toshiba Top 5 Metrology Perspectives Yuuichiro Yamazaki, Toshiba
Fujitsu Top 5 Metrology Perspectives Eiichi Kawamura, Fujitsu
SEMATECH 3D Interconnect  Top 5 Metrology Challenges Larry Smith, SEMATECH
SEMATECH Lithography Top 5 Metrology Challenges Bryan Rice, SEMATECH
SEMATECH FEP Top 5 Metrology Challenges Kah Wee Ang, SEMATECH
Panel Discussion: Supplier Community Perspectives on These Challenges Takeshi Kato, Hitachi; Kazuhiko Omote, Rigaku; DongSub Choi, KLA-Tencor; (TBD) Applied Materials

Collaboration in Manufacturing: The Diffusion of Innovation
The Diffusion of Innovation Sanjay Rajguru, ISMI 
ISMI’s Latest Initiative: The Mature Technology Fab Program Moritaka Nakamura, ISMI 
Equipment Productivity Forums: Collaboration for Equipment Productivity Gains Boyd Finlay, ISMI 
ESH Focus on Manufacturing Steve Trammell, ISMI 
Prognostics and Health Management (PHM) in Semiconductor Manufacturing David Stark, ISMI