SEMATECH Knowledge Series
SEMATECH Knowledge Series (SKS) meetings are unique opportunities to focus on accelerating solutions for critical challenges in the semiconductor industry.
For details about upcoming SKS meetings, please see Upcoming Meetings and Conferences.
SEMATECH Surface Preparation and Cleaning Conference
This conference—which brings together prominent researchers from the semiconductor industry and the university community— focuses on the current developments and ITRS challenges in advanced wafer and mask cleaning and surface preparation technologies. For over 11 years, industry experts representing IC manufacturers, suppliers, and research organizations from around the globe have gathered at the SPCC to present and discuss the industry’s best available data on mask and wafer cleans technologies and solutions including wafer front-end, wafer back-end, advanced mask, and environment, safety and health issues.
- March 19-21, 2012; Austin, TX
GSA/SEMATECH Memory+ Conference
This conference will feature senior executives from leading companies in the memory, logic and system markets to share their perspectives and insights regarding future memory applications, viable business models and collaborative opportunities among logic devices and memory technologies.
- April 19, 2012; Tokyo, Japan
International Technology Roadmap for Semiconductors (ITRS) Conferences
The ITRS continues to be revised in 2012, with a focus on the difficult challenges and technology requirements tables. These Overall Roadmap Technology Characteristics and working group materials will be updated as needed in the 2012 Update, to be released at the end of the year. The ITRS public conferences offer technologists and strategists from the manufacturing and supplier communities the opportunity to participate in building the next ITRS by providing input to the working group teams of industry and research experts who revise the semiconductor industry Roadmap.
- Summer Meeting - July 12, 2012; San Francisco, CA
- Winter Meeting - December 5, 2012; Hsinchu Taiwan
Executives and technical experts from SEMATECH and the semiconductor industry community will come together in keynote and in-depth technical sessions to share perspectives on progress and challenges in the areas of advanced devices, EUV lithography, 3D interconnects, and manufacturing productivity.
- Japan Symposium - June 26, 2012; Tokyo, Japan
- Taiwan Symposium - October 18, 2012; Hsinchu, Taiwan
- Korea Symposium - October 23-24, 2012; Seoul, Korea
SEMATECH 3D Interconnect Workshops
3D Electrostatic Discharge
As the semiconductor industry continues to move rapidly toward bringing 2.5D and 3D into volume production, manufacturers and researchers involved in the development and/or implementation of 3D TSV technology need a better understanding of the electrostatic discharge (ESD) risks associated with 3D processing, handling, test and assembly; and determine whether these risks require new standards and or guidelines. The goal of this workshop, held in conjunction with SEMICON West, is to more fully understand the nature of the ESD problem at both the design and manufacturing levels; examine the approaches in the industry that are currently being taken by fabless, IDMs, foundries, and OSATs; and identify any needs for new standards or guidelines.
- July 10, 2012; San Francisco, CA
Metrology for 3D Interconnect
Successful introduction of 3D interconnects will require that equipment suppliers and device manufacturers overcome the inherent challenges associated with measuring opaque films and high-aspect ratio features that dominate 3D architectures. Metrology for 3D architectures requires new techniques, revisiting and improving some older techniques, and breakthrough innovations to create new metrology tools. This workshop, held in conjunction with SEMICON West, focuses on how new and existing wafer metrology technologies can be utilized, modified or enhanced to measure and improve 3D interconnect processes.
- July 11, 2012; San Francisco, CA
Underfill Challenges for 3D Interconnect
3D Interconnect technology represents an industry-wide paradigm shift enabling the functionality, performance, and power consumption improvements required to maintain the semiconductor productivity roadmap. Underfill technology development is critical to overcome process yield, reliability, and thermal management detractors. The goal of this workshop is to describe the challenges the industry will face in the next 3-5 years and highlight the solutions in development by leaders in academia and industry.
- November 9, 2012; San Jose, CA
SEMATECH Advanced Mask Cleaning Workshop
This full-day workshop—held in conjunction with the BACUS Conference—provides a forum for SEMATECH members, mask and wafer cleaning suppliers, and researchers to discuss advancements in technologies and solutions applicable to advanced mask cleaning and surface preparation challenges. Topics include: mask lifetime dependencies on the cleaning process; radiation effects on Ru capped multilayers; e-beam inspection and particle removal; cleaning and storage; progressive defects; sub-20 nm particle removal; molecular contamination removal; the effects of cleaning on line-edge roughness and CD; mask inspection defect analysis; post-repair cleaning; and environmental approaches to mask cleaning. This workshop also addresses the application of novel cleaning technologies for the EUV mask cleaning, including plasma and cryogenic cleaning.
- September 10, 2012; Monterey, CA
SEMATECH International Symposium on Advanced Gate Stack Technology
The symposium will feature industry experts presenting their latest research in both invited and contributed talks and a discussion panel of representatives from major semiconductor device makers, equipment makers, and academia.
- October 3-4, 2012; Saratoga Springs, NY
International Symposium on Extreme Ultraviolet Lithography and Lithography Extensions
This symposium is the industry's premier conference to discuss and assess the worldwide status of EUVL technology and infrastructure readiness. The industry still faces a significant number of challenges for EUVL pilot line insertion in 2012/2013, as well as high-volume manufacturing (HVM) introduction in late 2013. These challenges include progress in key critical technology issues such as: mask yield and defect inspection/review infrastructure; long-term reliable source operation for HVM; and resist resolution, sensitivity, and line-edge roughness met simultaneously. Hosted by Imec in cooperation with SEMATECH and EIDEC, this year’s Symposium promises to be the most informative event, committed to addressing challenges and enabling solutions for advancing EUVL.
- September 30-October 4, 2012; Brussels, Belgium
Advanced Metallization Conference
As the industry continues to develop next-generation nanoscale interconnects incorporating novel ultra low-k materials, ultra-thin barrier and capping layers, the industry is continuously looking for significant performance improvements without sacrificing reliability. This conference will focus on both fundamental and applied research, advanced interconnect and gate stack materials, manufacturing and implementation challenges, unit process development, fully integrated technology, interconnect reliability, and IC wiring scaling.
- October 9-11, 2012; Albany, NY