SEMATECH Dictionary of Semiconductor Terms

A-Am | An-Az | B | C-Ch | Ci-Com | Con-Cz | D-De | Df-Dz | E-En | Eo-Ez | F-Fl
Fm-Fz | G | H | I | J-K | L | M-Mes | Met-Mz | N | O | P-Ph | Pi-Pq | Pr-Pz | Q | R
S-Se | Sh-So | Sp-Sta | Ste-Sz | T-Th | Ti-Tz | U-V | W-Z

"Sh-So"

shallow etch pits n		on a wafer, etch pits that are small and shallow in depth under high magnification greater than 200X. [ASTM F1241] Also called saucer pits. Also see haze.
shape n		for wafer surfaces, the deviation of a specified wafer surface relative to a specified reference plane when the wafer is in an unclamped condition, expressed as the range or total indicator reading (TIR) or as the maximum reference plane deviation (maximum RPD) within the specified fixed quality area (FQA). [SEMI M1-94]
sharpness n		the visual impression of distinctness in a photographic reproduction, such as the edge of an image; the subjective effect of the physical property acutance. [ASTM F127-84]
sheet resistance () ( or per square) n		of a semiconductor or thin metal film, the ratio of the potential gradient (electric field) parallel with the current to the product of the current density and thickness. [ASTM F1241]
shop floor control system n		a production control system for control of product movement through the manufacturing line and for measurement of manufacturing performance. [SEMATECH]
short		see bridge.
short flow n		A sequence of processing steps in a semiconductor fabrication facility that is a subset of the steps required to produce an integrated circuit product. A short flow processing sequence is usually an experiment to evaluate the performance of new or modified processes or equipments. [1994 National Technology Roadmap for Semiconductors]
short-term capability n		the process capability under controlled conditions over a brief period. [EIA 557]
short term exposure limit (STEL) n		in safety threshold limit values, the concentration to which workers can be exposed continuously for a short period of time without suffering from (a) irritation, (b) chronic or irreversible tissue damage, or (c) narcosis of sufficient degree to increase the likelihood of accidental injury, impair self-rescue, or materially reduce work efficiency, and provided that the daily threshold limit value, time-weighted average (TLV-TWA) is not exceeded. [SEMI S2-93]
short wavelength cutoff n		1 : in characterizing surface roughness by noncontact optical profilometry, the smallest spatial wavelength at which the measurement device will measure 50% of the true amplitude of the sinusoidal surface feature. [SEMATECH] 2 : in the roughness measurement of flat panel display substrate surfaces, a wavelength whose amplitude's attenuation ratio becomes 75% when the traced profile is passed through the low-pass wavelength filter that eliminates noise element. [Adapted from SEMI D7-94]
short-wire pitch n		the sum of conductor width and spacing between conductors for the short conductors on the first interconnect layer for transistor structures comprising subunits of the integrated circuit design. [1994 National Technology Roadmap for Semiconductors]
shot peening n		a process of introducing damage on the back surface of a silicon wafer by striking the surface with a stream of quartz or other hard beads carried in air or water. [SEMATECH]
should v		a term indicating that a provision is recommended as good practice but is not a requirement of a specification. [SEMI F1-90]
shoulder bend location n		in plastic or cerdip and cerpack types of semiconductor packages, the width of the shoulders between leads on opposite sides of the package, measured from the outermost point of the outer shoulder bend radius. [SEMI G14-88]
shoulder width intrusions		see protrusion.
show stopper n		a technical problem that, if not resolved, prevents further progress. [1994 National Technology Roadmap for Semiconductors]
shutdown n		the time required to put the equipment in a safe condition when entering a nonscheduled state. It includes any procedures necessary to reach a safe condition. Shutdown is included only in nonscheduled time. [SEMI E10-92] Also see equipment states.
shutoff valve n		a valve designed for and capable of positive closure to prevent flow within a piping system. Typical shutoff valves include, but are not limited to, manually-actuated, power-actuated, or spring-actuated fail-safe shutoff valves. Usually excluded are self-actuated valves, such as check valves, pressure regulators, flow controllers, and other devices that are not intended to provide positive shutoff for safety isolation. [SEMI F1-90]
SI n		abbreviation for the International System of Units (in its original French, le Système International d'Unités), which is a modernized metric system accepted as the standard by (among others) the American Society for Testing and Materials (ASTM), Semiconductor Equipment and Materials, International (SEMI), and the Institute of Electrical and Electronics Engineers (IEEE). [SEMATECH]
SIA		see Semiconductor Industry Association.
side n		1 : in quartz and high-temperature wafer carriers, either wall of a wafer carrier that is perpendicular to the wafer plane. [SEMI E2-93] 2 : in wafer transport equipment, the vertical planes not penetrated by any portion of the equipment. If a service connection such as a drain or an exhaust is brought out through a side, the boundary is defined by the nonservice portions of the equipment. [Adapted from SEMI E8-92]
sidebrazed adj		describes a ceramic dual inline package that has leads connected to the side of the package by brazing. [SEMATECH]
side load n		a result of bending a tube in a specified arc, consequently subjecting the tube fitting connection to a radial stress. [SEMI F9-92]
side porosity n		in plastic molding preforms, voids or holes with visible shape, size, and depth that are detected around a molding preform. [SEMI G49-93]
side-to-side misalignment n		among leads that are brazed to opposite sides of a package (for example, sidebrazed laminates), misalignment between the center lines of the leads on one side of the package to those of leads on the other side. [SEMATECH]
sigma ( or ) n		a Greek letter used in statistical analysis to signify standard deviation. [EIA 557]
sign n		a visual communication system that advises the observer of potential hazards that can cause accidental bodily injury, death, or property damage. A sign provides safety precautions, evasive actions, or other directions to eliminate or reduce the hazard to an acceptable level. [SEMI S1-90] Examples are safety sign, visual hazard alert, and alert.
signal integrity n		a condition in which signals can properly be resolved at their intended level in the presence of noise, interference, or crosstalk. [1994 National Technology Roadmap for Semiconductors]
signal-to-noise ratio n		the ratio of signal voltage at a given threshold to the background noise voltage. [SEMATECH]
signal word		see key word.
silane (SiH4) n		a colorless gas that is flammable and pyrophoric (capable of igniting spontaneously upon contact with air) and has a repulsive odor. Silane is used as a silicon source for the epitaxial deposition of single-crystal and polycrystalline silicon, for the low-temperature chemical vapor deposition of silicon dioxide, and for the chemical vapor deposition of silicon nitride films. It also is used for growth of amorphous silicon films. [SEMI C3.10-86]
silicide n		a silicon or polysilicon reaction with a metal to form a new compound. [SEMATECH]
silicon (Si) n		a brownish crystalline semimetal used to make the majority of semiconductor wafers. [SEMATECH]
silicon compiler n		a computer program capable of generating the design of a semiconductor circuit of the desired logic function from a description in a formal language. [SEMATECH]
silicon dioxide (SiO2) n		a passivation layer thermally grown or deposited on wafers. It is resistant to high temperatures. Oxygen or water vapor is used to grow silicon dioxide at temperatures above 900 degrees C. Silicon dioxide is used as a masking layer as well as an insulator. [SEMATECH] Also called quartz. Also see glass.
silicon nitride (Si3N4) (abbr. SiN) n		a passivation layer chemically deposited on a wafer at temperatures of between 600 degrees C and 900 degrees C to protect the wafer from contamination. Silicon nitride is also used as a masking layer and as an insulator. [SEMATECH]
silicon on insulator (SOI) n		a novel substrate for high-performance, low-power, and radiation-hard CMOS applications that offers process simplification, improved scalability, latch-up free and soft-error free operation, improved subthreshold slope, and drastic reduction in parasitic capacitances. At this writing, there are two manufacturing-oriented techniques to build SOI: SIMOX and bonded. [SEMATECH]
silicon on sapphire (SOS) epitaxial wafer n		a sapphire substrate combined with a silicon epitaxial layer deposited on it. [SEMI M4-88]
silicon probes n		electrical probes on an integrated circuit testing system that have been etched monolithically from a silicon wafer using a variation of integrated circuit processing technology. [1994 National Technology Roadmap for Semiconductors]
silicon source gas n		on a wafer, volatile or gaseous silicon compounds used as the epitaxial layer of material deposited. [SEMI M4-88] Also see epitaxy.
silicon tetrachloride (SiCl4) n		a corrosive, colorless liquid that has a sharp, pungent odor. It hydrolyzes rapidly to form hydrogen chloride. Silicon tetrachloride is used for epitaxial deposition of single-crystal silicon and for high-temperature chemical vapor deposition of silicon dioxide. It also is used in the plasma etching process. [SEMI C3.11-86] Also called tetrachlorosilane. Also see dry plasma etch.
silylation n		the process of incorporating silicon into a film. This may be done from the liquid or gas phases. [SEMATECH]
SIMOX n		a manufacturing-oriented technique to build silicon on insulator substrates. The process involves implanting oxygen and a high-temperature anneal to form the thin silicon film and the buried oxide. Abbreviation for separation by implantation of oxygen. [SEMATECH]
simulation n		representation of selected behavioral characteristics of one physical or abstract system by another system; for example, the representation of physical phenomena by means of operations performed by a computer system. [SEMATECH] Contrast analytical model.
single-block message n		a message sent in one block, which has up to 244 bytes of data. NOTE-In SECS-II, single-block messages must be sent as either a single block or a single packet. [SEMI E5-92] Contrast multiblock message.
single crystal n		a body of crystalline material that contains no large-angle boundaries or twin boundaries. [ASTM F1241] Also called monocrystal. Contrast polycrystalline.
single crystal silicon n		an arrangement of atoms in a solid that has perfect periodicity (that is, no defects). [SEMATECH]
single inline package (SIP) n		describes a package that is similar to a dual inline package but has a single line of leads on one side rather than on two sides. [SEMATECH] Also see dual inline package.
single layer alumina metallization (SLAM) n		generally, a chip carrier package that does not have any cavities for die attach or wire bonding. Either such packages are sealed using cup shaped lids, or the die and wire bonds are coated with a resin. [SEMI G33-90]
single segment n		a single functional pattern formed by optical reduction from artwork. It is stepped and repeated to form an array. [ASTM F127-84]
sinter v		to react deposited aluminum with silicon to ensure good adhesion and to reduce radiation damage sometimes associated with aluminum deposition. [SEMATECH]
site n		on the front surface of a wafer, a rectangular area, the sides of which are parallel and perpendicular to the primary flat or to the notch bisector and the center of which falls within the fixed quality area (FQA). [SEMI M1-94]
site array n		a set of contiguous sites. [SEMI M1-94]
site flatness n		on a wafer, the total indicator reading (TIR) or the maximum focal-plane deviation (FPD) of the portion of a site that falls within the fixed quality area (FQA). [SEMI M1-94]
skewness		see pitch error.
SLAM		see single layer alumina metallization.
slave n		the block-transfer designation for the host computer. NOTE-The equipment is designated as the master. This naming convention is based upon the assumption that the equipment is less able to store messages than the host. [SEMI E4-91]
sled n		a quartz structure with which quartz carriers that contain wafers are moved into, and out of, a furnace. [SEMATECH]
sleek n		in flat panel display substrates, a very shallow scratch on the polished surface that is sometimes invisible when the viewing angle is changed. [SEMI D9-94]
slice		see wafer.
slip n		in semiconductor wafers, a process of plastic deformation in which one part of a crystal undergoes a shear displacement relative to another in a manner that preserves the crystallinity of each part of the material. DISCUSSION-After preferential etching, slip lines are evidenced by a pattern of one more more parallel straight lines of dislocation etch pits that do not necessarily touch each other. On \|111\| surfaces, the group of lines are inclined at 60 degrees to each other; on \|100\| surfaces, they are inclined at 90 degrees to each other. [SEMI M10-89 and ASTM F1241] Also see pit.
slip line n		a step occurring at the intersection of a slip plane with the surface. [ASTM F1241]
slip plane n		the crystallographic plane on which the dislocations forming the slip move. [ASTM F1241]
slot n		1 : the area in which a wafer is situated within a wafer carrier. [SEMATECH] 2 : a two-sided support for a standard wafer carrier when the carrier is oriented with its axis in a vertical attitude. [SEMI E22-91] 3 : in cluster tools, a wafer location within a cassette module associated with the function of wafer I/O. Wafers enter or leave the intratool environment through slots. Generally, a slot, through its slot group, corresponds to a carrier location within a wafer carrier. [SEMATECH]
slot group n		in cluster tools, a logical collection of slots within a cassette module. A slot group, in general, corresponds to a carrier, containing the same number of slots as there are carrier locations in the corresponding carrier. [SEMATECH]
slot spacing n		in quartz and high-temperature wafer carriers, the distance from the center line of the first slot on one end to the center line of the slot on the other. [SEMI E2-86] Also see slot.
slug marks n		in the production of stamped leadframes, random dents in the leadframe caused by foreign materials; for example, metal filings or imperfections in the rolling or stamping punches. [SEMI G2-94]
small scale integration (SSI) n		the placement of between 2 and 10 active devices on a single die. [SEMATECH]
SMIF		see integrated standard mechanical interface.
SMS-context n		a specification of the service elements of SECS message service (SMS) and semantics of communication to be used during the lifetime of an application association. [SEMI E13-91]
SMS-provider n		that part of an application entity that conceptually provides the SECS message service (SMS) through the exchange of SMS protocol data units (PDUs). [SEMI E13-91]
SMS-user n		that portion of the application process that conceptually invokes the SECS message service (SMS). [SEMI E13-91]
smudge n		dense local area of contamination usually caused by handling or fingerprints. [SEMI M1-94 and ASTM F1241] Also see dirt.
snowball n		on a semiconductor wafer, a track with the appearance under magnification of a snowball rolled through snow. [ASTM F1241]
sodium dodecyl sulfate (SDS) n		in determining surface associated biofilms of ultrapure water distribution systems, a common anionic detergent used as a biofilm release agent to obtain sample suspensions. [SEMATECH]
sodium hydroxide (NaOH) n		1 : a strong, caustic base in the form of white crystals. [SEMI C1.22-90] 2 : a caustic material used as an etchant for polysilicon and silicon nitride. [SEMATECH]
soft bake n		heat treatment of resist-coated wafers (typically at 80-100 degrees C) to drive off solvents before the wafer is exposed. [SEMATECH]
soft error n		a memory-state error caused by a process that produces no permanent alteration of the physical condition of the device. [SEMATECH]
software engineering n		the systematic approach to the development, operation, maintenance, and retirement of software. [SEMATECH]
software/hardware co-desig		see hardware/software co-design.
software interlock n		data exchange between two programs in order to verify that interlock conditions are met. [SEMATECH]
software process improvement (SPI) n		a structured approach to improving the quality of a corporation's software products through increasing their software development and maintenance capabilities along the lines defined by the capability maturity model developed by the Software Engineering Institute. [SEMATECH]
SOI		see silicon on insulator.
solder		1 v : to join two metals together using a metal alloy that melts, by industry convention, below 427 degrees C (800 degrees F). The two metals to be joined do not melt but may either show slight surface alloying with the solder or, in the case of plated components, the plating may become alloyed into the solder. [SEMATECH] Contrast braze. 2 n : a metal alloy with a melting point below 427 degrees C (800 degrees F). Tin/lead alloys are the most common alloys used for soldering. 80%/20% gold/tin alloy is often used to solder metal covers to metallized or metal seal rings on ceramic packages. [SEMATECH] Also see preform.
solvent n		a substance capable of dissolving another substance, or substances, to form a solution. Examples are isopropyl alcohol, methyl alcohol, and xylene. [SEMATECH]
solvent residue n		1 : a type of dirt found on wafer surfaces after solvent evaporation from the surface. The residue either is left by the solvent itself or is material that the solvent has removed from the surface and redeposited. [ASTM F1241] 2 : type of film found on wafer surfaces after solvent evaporation from the surface. [SEMI M10-89]
soot n		agglomerations of particles of carbon impregnated with "tar," formed in the incomplete combustion of carbonaceous material. [ASTM D1356 REV A-73]
sori n		the difference between the maximum and minimum distances between a front-side reference plane and the surface of a wafer that is not chucked. The reference plane is chosen either as a means of minimizing the difference (sori) or as a least-squares fit to the front surface. [SEMI M1-90]
sort yield n		ratio of total number of good products (actual) to the potential number of good products. [SEMATECH]
SOS		see silicon on sapphire.
source n		one of the three major components of a CMOS transistor. [SEMATECH]
source code n		input to a compiler or assembler in a programming language usable by a machine-code translator. [SEMATECH]

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