3D Interconnects: Meet the experts
SEMATECH's 3D Program is led by a strong team of diverse talents with experience in key areas needed to make manufacturable 3D interconnects a reality.
Sitaram R. Arkalgud, Ph.D., is the director of SEMATECH’s 3D Interconnect Program. Arkalgud has directed SEMATECH’s Interconnect division for three years while on assignment to SEMATECH from Qimonda/Infineon Technologies. Prior to his assignment at SEMATECH, he was Infineon’s Director of the MRAM Development Alliance between Infineon and IBM, and worked as a technology officer for the Memory Products Division and product manager for Ferroelectric RAM. Previously, he was at Motorola, working for nine years in several advanced logic and memory projects. He holds a doctorate and master’s degree in materials engineering from Rensselaer Polytechnic Institute, and a bachelor’s degree in metallurgical engineering from Karnataka Regional Engineering College, Suratkal, India. He is author of many publications and presentations, and holder of 14 patents.
Sharath Hosali, Ph.D., is a Member of Technical Staff focusing on development of unit processes for 3D interconnects. Prior to joining SEMATECH, he worked for Philips Semiconductors as a SEMATECH assignee developing processes for copper ultra low-k interconnects using CMP, CVD, UV-cure, etch, and ash. He also served as a senior scientist at Rodel for five years developing products for copper and STI applications. He holds a doctorate in Materials Science and Engineering from Rensselaer Polytechnic Institute and a bachelor of technology degree from the Indian Institute of Technology in Madras, India.
Greg Smith, Ph.D., is a Senior Member of Technical Staff working on 3D integration. He has been with SEMATECH for eight years in low-k interconnect, front end baseline integration, and management of a unit process group. Following the completion of a doctorate in Physics at Ohio State University, he spent 13 years at Texas Instruments on flat panel display development, CMOS processing, and the Digital Light Processor. For the next five years, he managed thin film deposition in Advanced Technology Development at ST Microelectronics, then served as Process Engineering Manager of Carrollton Fab 6. He holds over 20 patents.
Larry Smith, Ph.D., is a Member of the Technical Staff, responsible for 3D cost and yield modeling and reliability. He previously worked on copper low-k reliability and process integration. Prior to joining SEMATECH, he worked on high density interconnect for packaging applications, managing the design group for thin-film-on-laminate BGA substrates at Kulicke & Soffa, and managing programs on multi-chip packaging at MicroModule Systems, Dell Computer, and MCC. He received his Ph.D from the University of Illinois-Urbana.
