Materials and Processes
Front End Processes (FEP)
FEP at SEMATECH focuses on the materials, tools and processes to enable the extension of CMOS Technology. Near term deliverables include driving equivalent oxide thickness (EOT) to 0.8 nm while meeting specifications for threshold voltage (Vt), mobility and other parameters, and ensuring metal gates are manufacturing-worthy by 2006. FEP also works on electrical characterization methodologies and tools for high-k/metal gate devices and non-planar CMOS devices. Working with member companies, the SRC, leading universities and national labs, FEP ensures that the needed materials, tools and processes are available to enable effective scaling to the end of the International Roadmap for Semiconductors (ITRS).
Programs
- Advanced gate stack
- High-k dielectric
- Metal gate
- Non-classical CMOS
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- SEMATECH Engineers Reveal Further Details of Trailblazing Work on Practical High-K Metal Gate Systems for 45nm And Beyond
- Solutions Emerging for Wafer Cleaning at 45 nm and Beyond
- SEMATECH to Continue Pursuing Planar Transistor Scaling Strategy; But Will Investigate FinFETs as an Alternative
- SEMATECH Develops Dual Metal Gates for high-k CMOS Devices; Completes Quest with pMOS Breakthrough
Interconnect
Responding to challenges in the ITRS, SEMATECH’s interconnect work focuses on delivering materials and processes to demonstrate keff ≤ 2.1 by the end of 2007 for the 32 nm node. We are also exploring the viability of 3D-TSV (through silicon via) interconnects.
Programs
- Advanced low-k materials
- Copper low-k development
- 3D-TSV interconnect
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