Cleanroom

Materials and Emerging Technologies

As semiconductor geometries edge ever-further into nanoscale dimensions, new materials and the technologies to support them take on much greater importance. From disruptive gate stack and channel designs to breakthrough metrology and ultra-low leakage capabilities, new solutions are needed to contend successfully with the inexorable laws of molecular physics.

SEMATECH’s Front End Processes (FEP) Program is helping meet these challenges with projects aimed at ensuring that critical materials, tools and processes are available in time for effective scaling to the limits envisioned by the International Technology Roadmap for Semiconductors (ITRS). These projects include:

  • Advanced CMOS scaling with focus on ultra-shallow junctions (USJs), low R contacts, and high mobility channels
  • Non-planar CMOS, including fin-shaped field-effect transistors (finFETs) and nanowires
  • Advanced dielectrics and electrodes
  • High-k dielectrics and metal electrodes for gate stacks and memories
  • Disruptive and emerging memory technologies
  • Physical characterization of materials and interfaces, and development of novel characterization methodologies
  • Reliability assessment

Recent Advancements

Recently, SEMATECH's FEP engineers demonstrated for the first time that hafnium-oxide films with a zero low-k silicon-oxide interface scale better than exotic higher-k materials, providing a practical, scalable option for manufacturers. FEP also delivered a systematic study explaining low drive currents in germanium-based n-channel metal-oxide semiconductor FETs (MOSFETs).

Other advancements include:

  • Demonstration of significant reductions in Schottky barrier height and contact resistance, enabling continued enhancement of device performance beyond the 45 nm technology node. Contact resistance in source/drain regions, which comes from a relatively high Schottky barrier between n-type doped Si and nickel silicide is one of the most pressing concerns of advanced CMOS technology.
  • Partnering with Metrosol, Inc. to develop and demonstrate an inline metrology system based on vacuum ultraviolet spectroscopic reflectometry (VUV-SR). This platform is will be able to provide the highly accurate characterization needed for inline metrology of advanced logic and memory applications for future technology generations.
  • Delivering game-changing channel work utilizing new materials such as silicon-germanium (SiGe), indium-gallium-arsenide (InGaAs), and indium arsenide (InAs). Illustrating this effort was a paper delivered at the 2009 VLSI Technology Symposium in Kyoto, Japan on key parameters for controlling threshold voltage variation and strain maintenance of gate-first SiGe channel pMOSFETs.

Future Goals

Recognizing that disruptive technology must become the norm for the industry to keep pace with Moore’s Law, FEP has adopted an ambitious strategy for the next five years. Major goals include the following.

  • Low-power solutions involving:
    • low standby power/low operating power,
    • low positive supply voltage for high-performance transistors
    • nano-electro-mechanical switches (NEMS),
    • Subthreshold slope transistors for electronics with extremely low power
  • Disruptive scaling for silicon and disruptive technology for III-V metals, fins, and nanowires
  • High mobility channels utilizing silicon with III-V elements and graphene, with low leakage and low contact resistivity (Rcon)
  • Focus on disruptive scaling for memory technologies, utilizing Resistance based Random Access Memory (ReRAM) and Spin Transfer Torque RAM (STTRAM)